|First use of Direct Memory Access (DMA) whereby I/O operations could proceed independently of instruction processing thereby greatly improving overall system performance|
Why it's important: Direct Memory Access or DMA was a substantial improvement in design, programming, and performance of computer systems and I/O operations. I/O operations using DMA could occur without stopping the instruction processing during mechanical operations of peripheral devices. Special sequencing that required detailed knowledge of the mechanical timing of peripherals by programmers was incorporated into the logic structure of the DMA capable peripheral device controller. Data could be transferred to or from any location in main memory, eliminating the need for special I/O memory buffers and reducing memory to memory relocation of data buffer contents. In many implementations, multiple DMA enabled peripherals could be transferring data simultaneously, as their combined data rates were usually a modest fraction of main memory bandwidth. Buffers in the peripheral controller synchronized transfers with the main memory cycles and enabled devices to interleave their transfers to memory. Thus, many I/O operations could be overlapped for greatly improved system throughput. In some systems, priority schemes gave precedence to transfers from high data rate synchronous devices such as drums over low transfer rate asynchronous devices such as card readers. This innovation had a major impact on the design of modern computers including the development of interrupts and data channels.
Discussion: "Overlapped I/O" was a major event in the design of I/O systems, particularly as relevant to magnetic drum, disk, and tape subsystems. As 'overlapped I/O" existed prior to DMA, the appropriate title for this event is "Peripheral Device DMA".
From UNIVAC and IBM manuals (see Bitsavers.org) the time of interest for their systems is before 1958/9. Specifically the UNIVAC 1105 vs the IBM 709. It would also appear that these two machines are contestants for "first channel". A very good reference for this topic is by Mark Smotherman at http://www.cs.clemson.edu/~mark/io_hist.html see also Smotherman references in this paper, http://portal.acm.org/citation.cfm?doid=71302.71303. However, he omits the 1105 from his history. DMA did exist in two military systems prior to these commercial machines. Smotherman notes:
"The DYSEAC also appears to be the first computer to provide DMA, although IBM was granted a patent for DMA cycle-stealing on the SAGE system (US 3,319,230 Astrahan, et al., 'Data Processing Machine Including Program Interrupt Feature,' filed Sept. 1956 and granted May 1967). (The SAGE project started in 1952, and I cannot yet determine the date of the first use of DMA in the design.)"There is a SAGE programming manual in the CHM collection and a couple of DYSEAC publications of unknown content.
Neither DYSEAC (Army) or SAGE (Air Force) were commercial computers, so depending on ship dates of 1105 (1958?) vs IBM 709 (1958) may go the honors of first overlapped I/O. The 709 I/O units were called "Data Synchronizer Units" and six of these "were added to the 704 to make it a 709" (Hockney, 1988) From the attached 1105 excerpt, it seems the 1105 or the 709 were contemporaneous, with the edge going to the 709.
“One limitation of the Univac 1103 and the IBM 704 was that the CPU directly controlled all I/O operations, reducing the amount of time available for computation. To free the processor from this burden, IBM developed a buffered I/O system on its 709 computer, in which data channels attached to the memory could perform I/O at the same time as the processor was doing computation. The first 709 was delivered in late summer 1958. A parallel development at Sperry Rand produced the 1105, which was completed in fall 1958. The 1105 was essentially an 1103 with a new I/O system.” [Sperry Rand’s First-Generation Computers, 1955-1960: Hardware and Software, George T. Gray, Georgia Technology Authority, Ronald Q. Smith, Unisys Corporation, IEEE Annals of the History of Computing, Oct/Dec 2003, pp. 20-34]
Bashe et al indicate, “… when 709 deliveries began in mid-1958.” [IBM’s Early Computers, 1986]
There was a major lawsuit over overlap I/O between IBM and UNIVAC and IBM won, likely because of the SAGE patent(S).
Here are some factoids about I/O from the bitsavers collection:
UNIVAC I - 1952 manual copyright - One instruction could swap the contents of the separate 60 word tape buffer (Hg delay line) with memory (Hg delay line). A tape operation could be initiated and completed simultaneously continued program operation. Tape data transfers were independent of the instruction processing. Only the console typewriter was a direct attach I/O that stalled the instruction processing. In a way U-I tapes are "overlapped I/O" since the total cpu lost processing time was just the memory cycle time of the machine times the number of data words transferred. However, since I/O was to/from a separate buffer memory, and only for tape, this is disqualification. An essential feature of DMA I/O is that data ends up (almost) anywhere in primary memory. Whether interrupts are a necessary feature of DMA I/O may be subject to debate and I argue they aren't as the 709 did not have interrupts. It doesn't matter if the I/O DMA address was part of the CPU logic or part of the peripheral controller in order to qualify.
ERA 1103 - manual copyright 1953 -36 bit machine, two address, electrostatic and drum memory, synchronous programmed I/O but other instructions could be executed between some I/O transfers. However, for tapes, "the computer is fully occupied during execution of the block transfers"
UNIVAC 1103A - 1958 manual copyright - 36 bit machine, core, drum and tape plus many other direct attach peripherals. Some I/O was synchronous, i.e. the paper tape punch would hang the cpu for the 16.7msec punch time. The I/O data, in or out, was provided through the X register and interlocks were appropriate to insure data was read or written as needed by the peripheral. However, an interrupt capability was also provided to permit overlapped programming with I/O transfers. A fixed memory location was executed upon interrupt and the X register contents saved and replaced with the I/O data and then restored and a jump was executed to the running program. The REPEAT instruction is cautioned as a problem as it could not be interrupted until completion and therefore the "receptive time" of the I/O device could be exceeded prior to the interrupt routine servicing the I/O data needed. Historians seem to agree that 1103A is first shipment of the interrupt concept.
UNIVAC 1105 -1958 preliminary manual copyright - see attached pdf. Two channels of fully overlapped I/O, a max of 10 tapes per channel. Introduced 1958, references to shipping in 1959.
UNIVAC 1107, shipped 1963, The 1107 had 16 channels of fully overlapped I/O, each channel's I and O memory location and increment or decrement memory address modifier of 16 bits(!) in 16 separate 36 bit registers. There were 128 addresses/registers of 667nsec cycle time thin film memory. I note that the 1103 REPEAT problem existed in the 1962 design of the 1107 in a different manner. REPEAT on that machine was interruptible (there were 16 registers for REPEAT counts!) and the machine state was stored, but not always correctly restored, so we disabled the REPEAT instruction on the CASE machine. If I remember correctly, the 1107 paper tape punch was still a weird synchronous I/O device. The 1107, although 36 bit, was a significantly different architecture (single address) than the 1103's.
IBM 701 - 1953 manual copyright - 36 bit machine, electrostatic & drum memory, tapes, printer and card direct attached. All I/O data provided synchronously via the MQ register by software. Some mechanical actions (card/print) could be initiated and program continued until data was required but system would hang at this point until data was provided. For tape the machine stalled waiting for MQ register reloads.
IBM 704 - 1954 manual copyright - 36 bit, core, drum, and tapes. "information flows between the input-output components through the central processing unit". I/O data is program written or read through the MQ register which is integral to the CPU data paths. There are some esoteric means to have some instructions executed while waiting for the I/O, but no practical means to have overlapped I/O..
IBM 709 - circa 1958 - 36 bit core, drum and tapes - bitsavers does not have an IBM 709 programming or principals of ops manual. There are copies of the appropriate manuals in the CHM collection, but these are not online, so I could not refer to them.
IBM 1401 - circa 1960 - all I/O data runs through the main registers and the machine stalls. Some machines were later field modified to have limited "overlap", a horrendously complex field mod, that only allowed instructions to be processed during known periods when peripheral devices had mechanical motion but no data transfer.
ElectroData (Burroughs) 205 - prelim manual 1955 - drum memory, tapes added later after Burroughs took over. Direct programmed I/O only.
The history of interrupts is closely related to this topic:
see McCarthy http://www-formal.stanford.edu/jmc/history/timesharing/timesharing.html (interrupts as they relate to timesharing, not I/O. McCarthy is sometimes credited incorrectly with the invention of the interrupt)
see Norman Hardy's http://cap-lore.com/Hardware/int.html
for a broad overview of the history of interrupts, see http://www.cs.clemson.edu/~mark/interrupts.html
Additional Information: See incorporated references
Provenance note: This article was authored by Grant Saviers; his last approved revision is Version 11